This invention relates to a packaged, microelectronic device having a plurality of microelectronic elements in the form of integrated circuit chips in a stacked relationship with each other.
In integrated circuit devices, it is at times desired to form a packaged device that has one smaller semiconductor die or chip attached to and interconnected with another semiconductor die or chip. Such packaged devices are often referred to as stacked-chip packaged devices. Such packages are desirable and find many applications. One such application is in programmable logic devices (PLDS). For example, it is desirable to add memory to a logic chip such as a digital signal processor (DSP) chip, a central processing unit (CPU) chip or a field programmable gate array (FPGA) chip.
U.S. Pat. No. 6,452,259 to Akayama describes such an LSI (large scale integration) integrated circuit device. Referring to FIG. 1, a cross-section of an LSI device is illustrated. The LSI 2 is a stacked chip 4 supported by package substrate 12. The stacked chip 4 is a single body that consists of a first chip 8 laminated to a second chip 6. In one example, the first chip 8 has a field programmable gate array (FPGA) function and the second chip has a central processing unit (CPU) function. First chip 8 is electrically interconnected to second chip 6 by bonding together opposing contacts 6a and 8a, and 6b and 8b. On the periphery of larger chip 8 there are a plurality of contact pads 10. Through these contacts, interconnection between the LSI and other devices is achieved.
The stacked chips 6 and 8 are supported by a package 12. A pad 14 on package 12 is interconnected with the pad 10 on the chip 8 by the bonding wire 16. In addition to being supported by package 12, the stacked chip structure 4 and the bonding wire 16 are sealed by a material such as epoxy resin.
The advantages of forming such LSI devices are numerous. First, such devices have the footprint of a single device and thus take up less area when placed on a circuit board and assembled with other components. Also, by being interconnected in the stacked configuration in a single package, communication delays that would result if the chips were packaged separately from one another and interconnected in a more conventional manner (e.g. traces on a printed circuit board) are avoided.
However, such devices present many packaging challenges. Chief among them is the challenge of accurately interconnecting the contacts of the chips. This is due to the extremely fine pitch between contacts. Thus, while stacked chip packaging continues to be viewed as an attractive way to package PLDS, improvements in methods for achieving interconnection between the chips is sought.